Schematic Reference

FAIRCHILD SEMICONDUCTOR FMS6418B ELECTRONIC DIAGRAM

This part consists of a triple 6th order filter with selectable 33MHz or 8MHz frequencies. At any given time, the input signal’s DC levels must be between 0.0V and 1.3V to utilize the optimal headroom and to avoid clipping on the outputs. The 220 ?F capacitor coupled with the 150 ? termination forms a high pass filter that blocks the DC while passing the video frequencies and avoiding tilt. Lower values such as 10 ?F would create a problem. By AC coupling, the average DC level is zero. Thus, the output voltages of all channels will be centered around zero. Alternately, DC coupling the output of the FMS6418B is allowable. There are several trade-offs: The average DC level on the outputs will be 2V; each output will dissipate an additional 40mW nominally; The application will need to accommodate a 1V DC offset sync tip; And it is recommended to limit one 150 ? load per output.